Introduction: Why the SIRA36DP-T1-GE3?
This tutorial centers on the Vishay Siliconix SIRA36DP-T1-GE3, a 30V, 40A N-channel MOSFET in a PowerPAK SO-8 package. What makes it exceptional for hands-on learning is its extremely low on-resistance (R_DS(on) = 2.1 mΩ typical at V_GS = 10V) combined with a compact, thermally efficient package. The PowerPAK SO-8 has an exposed pad that solders directly to the PCB, allowing heat to flow into the copper plane—critical for high-current switching. It also features a logic-level threshold (V_GS(th) = 1.2V to 2.2V), meaning it can be driven directly from a 3.3V or 5V microcontroller without a separate gate driver IC. This makes it ideal for a practical, low-cost, high-efficiency load switch or motor driver.
Design Requirements & Specifications
We will design a 12V, 10A continuous load switch with the following specifications:
- Input voltage: 12V ±10% (10.8V to 13.2V)
- Output current: 10A continuous, 15A peak for 1 second
- Switching frequency: 100 Hz (slow, to minimize EMI and gate drive losses)
- Control signal: 3.3V CMOS logic (ON/OFF)
- Target efficiency: >98% at 10A (i.e., total power dissipation < 2.4W)
- Ambient temperature: 25°C, PCB with 2 oz copper, 20 mm x 20 mm thermal pad area.
Step-by-Step Design Process with Calculations
1. Determine worst-case power dissipation. At 10A, the maximum R_DS(on) at 25°C is 2.1 mΩ. But R_DS(on) increases with temperature; at 125°C it roughly doubles to 4.2 mΩ. So, P = I² × R = 10² × 0.0042 = 0.42W. This is negligible for the package’s thermal capability (junction-to-ambient thermal resistance ~40°C/W with a proper pad).
2. Check the 3.3V gate drive. At V_GS = 3.3V, the R_DS(on) is not specified as a maximum, but the typical value from the datasheet curve is about 3.5 mΩ (verify with Figure 5 in the datasheet). This gives P = 10² × 0.0035 = 0.35W—still fine. However, to guarantee the lowest possible resistance, we can add a simple gate driver or use a 5V rail if available. For this tutorial, we’ll drive with 3.3V and accept the slightly higher R_DS(on).
3. Calculate gate charge and switching losses. Total gate charge (Q_g) at 10V is ~48 nC. At 100 Hz, the switching loss is negligible: P_sw = 0.5 × V_in × I_load × (t_rise + t_fall) × f_sw. With t_rise/t_fall ~ 50 ns each, P_sw = 0.5 × 12 × 10 × 100e-9 × 100 = 0.006W. Not a concern.
4. Select the gate resistor. To limit inrush current into the gate and reduce ringing, add a 10Ω series resistor. This creates an RC with the input capacitance (C_iss ~ 3.8 nF), giving a time constant of 38 ns—fast enough for 100 Hz.
Component Selection Rationale (Complete BOM)
- Q1: SIRA36DP-T1-GE3 (the MOSFET).
- R1: 10Ω, 0.25W (gate series resistor) – limits gate current spikes.
- R2: 100kΩ (pull-down resistor from gate to source) – ensures the MOSFET is off if the MCU pin floats or during power-up.
- C1: 100 µF, 25V electrolytic (input bulk capacitor) – stabilizes the 12V rail against load transients.
- C2: 1 µF, 25V ceramic X7R (input high-frequency bypass) – placed close to Q1’s drain.
- C3: 10 µF, 16V ceramic X7R (output capacitor) – reduces voltage droop on the load.
- D1: 1N5819 Schottky diode (freewheeling diode) – only needed if the load is inductive (e.g., a motor or relay). For a resistive load, omit it. We’ll include it for robustness.
- U1: (Optional) SN74LVC1G125 buffer – if you want to boost the 3.3V gate signal to 5V for lower R_DS(on). But for this tutorial, we drive directly.
- PCB thermal pad: Use a 20mm x 20mm copper area on the top and bottom layers, connected with vias.
Simulation Tips and What to Look For
Use LTspice or PSpice with the vendor’s SPICE model (download from Vishay’s website). Key things to simulate:
- Gate voltage waveform: Check for ringing or slow rise time—adjust R1 if needed.
- Drain-to-source voltage during switching: Look for overshoot beyond 30V. If you see spikes, add a snubber (e.g., 1Ω + 1nF in series from drain to source).
- Steady-state temperature: Use the thermal model in simulation to verify junction temperature stays below 125°C. At 0.42W and 40°C/W, junction temp = 25 + 0.42×40 = 42°C—very safe.
- Load transient response: Simulate a step from 1A to 15A and watch the output voltage droop. Your 10 µF output cap should limit droop to ~0.1V for a 1 ms pulse.
Prototype Build and Testing Methodology
1. PCB layout: Place Q1 with the exposed pad on a large copper island. Use multiple vias (0.3mm) under the pad to stitch top and bottom copper. Keep the gate trace short and away from the drain trace to avoid coupling.
2. Soldering: Use a hot-air rework station or a reflow oven. If hand-soldering, use a soldering iron with a large tip and add flux to the pad. Ensure the exposed pad is fully wetted—this is critical for thermal performance.
3. Functional test: Apply 12V input, then toggle the gate with 3.3V from a bench supply. Measure the output voltage with a multimeter—it should be within 50 mV of 12V.
4. Load test: Connect a 1.2Ω, 100W power resistor (for 10A). Monitor the MOSFET case temperature with a thermocouple. After 5 minutes, it should stabilize below 50°C.
5. Switching test: Drive the gate with a 100 Hz square wave from a function generator (3.3V amplitude). Use an oscilloscope probe on the drain to observe clean edges without excessive ringing.
Performance Verification and Optimization
- Measure on-resistance directly: Force 10A through the load and measure V_DS with a 4-wire Kelvin connection. R_DS(on) = V_DS / 10A. Expect ~2.5 to 3.5 mΩ at 3.3V gate drive.
- Efficiency calculation: Efficiency = (V_out × I_out) / (V_in × I_in). At 10A, with 0.35W loss, efficiency = (12V × 10A) / (12V × 10A + 0.35W) = 99.7%.
- Optimization: If you need lower R_DS(on), add a 5V gate bias. Or, reduce the gate resistor to 4.7Ω for
